The present invention relates to integrated-circuit processing and, more particlarly, to an improved method for fabricating an integrated circuit with multiple metalization layers. A major objective of the present invention is multi-metalization integrated circuit manufacture with higher yields and more reliable resulting products.
Much of recent technological progress is associated with the increasing integrated circuit miniaturization made possible by the smaller feature sizes achieved by advances in semiconductor processing. Once the basic circuit elements, e.g., transistors, are fabricated, they must be interconnected to provide integrated functionality. Interconnections are typically made in photolithographically patterned metalization layers. As features become smaller, circuit density increases. To take advantage of the increased density, more complex routing is required to maximize functionality.
The demands for more complex routing are accommodated by using multiple metalization layers, typically patterned from deposited aluminum. These layers are electrically insulated from each other by "intermetal" dielectric layers, usually of silicon dioxide of "oxide". Apertures are patterned in an oxide layer to accommodate electrical connections ("vias") between the metalization layers. When a metal is deposited over the via apertures, the via apertures are filled with the interconnecting metal.
Once a metalization layer is deposited, subsequent processing must be designed to avoid melting the metal. Otherwise, the metal can melt and flow, impairing the metal pattern's precision. Metal flow can result in shorts or unacceptably high cross talk in operation, and any number of other unintended results. In particular, the presence of aluminum practically limits subsequent processing temperatures to about 450.degree. C. or less.
This constraint applies to the intermetal dielectric. Accordingly, a relatively low-temperature chemical-vapor deposition (CVD) technique is available to deposit oxide on aluminum. One problem with unenhanced CVD is that it is slow. The slowness diminishes manufacturing throughput, which, in turn, increases manufacturing costs.
The presence of plasma increases the CVD rate. Accordingly, plasma-enhanced chemical-vapor deposition (PECVD) is used to attain higher manufacturing throughput while meeting thermal constraints on processing. Unfortunately, there is some evidence that PECVD can induce functional defects in some devices, adversely affect manufacturing yield. In addition, some apparently functional devices fail after repeated use. What is needed is an integrated circuit manufacturing method that provides the advantages of PECVD while providing greater yields and devices of greater reliability.